08490109.pdf (3.92 MB)
0/0

Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations

Download (3.92 MB)
journal contribution
posted on 29.03.2019 by Farid Kenarangi, Inna Partin-Vaisband
Modern power analysis attacks (PAAs) and existing countermeasures pose unique challenges on the design of simultaneously secure, power efficient, and high-performance ICs. In a typical PAA, power information is collected with a monitoring circuit connected to the compromised device. The non-typical voltage variations induced on a power distribution network (PDN) by such a malicious probing are sensed with on-chip sensors and exploited in this paper for detecting PAAs in real-time using statistical analysis. A closed-form expression for the voltage variations caused by malicious probing is provided. Guidelines with respect to the PDN characteristics and number of sensors are proposed for securing power delivery. The PAA detection system is designed in a 45-nm standard CMOS process. Based on the simulation results, a PAA on an IBM benchmarked microprocessor is detected with the accuracy of 88% with 30 on-chip sensors. Power overhead of 0.34% and 14.3% is demonstrated in, respectively, the IBM microprocessor and a typical advanced encryption standard system. In a practical cryptographic device, security sensitive PDN regions can be identified, significantly reducing the number of the on-chip sensors.

History

Publisher Statement

© (2019) IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

Citation

Kenarangi, F., & Partin-Vaisband, I. (2019). Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(2), 769-781. doi:10.1109/TCSI.2018.2872567

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Language

en_US

issn

1549-8328

Issue date

01/10/2018

Exports