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Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations

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journal contribution
posted on 29.03.2019, 00:00 by Farid Kenarangi, Inna Partin-Vaisband
Modern power analysis attacks (PAAs) and existing countermeasures pose unique challenges on the design of simultaneously secure, power efficient, and high-performance ICs. In a typical PAA, power information is collected with a monitoring circuit connected to the compromised device. The non-typical voltage variations induced on a power distribution network (PDN) by such a malicious probing are sensed with on-chip sensors and exploited in this paper for detecting PAAs in real-time using statistical analysis. A closed-form expression for the voltage variations caused by malicious probing is provided. Guidelines with respect to the PDN characteristics and number of sensors are proposed for securing power delivery. The PAA detection system is designed in a 45-nm standard CMOS process. Based on the simulation results, a PAA on an IBM benchmarked microprocessor is detected with the accuracy of 88% with 30 on-chip sensors. Power overhead of 0.34% and 14.3% is demonstrated in, respectively, the IBM microprocessor and a typical advanced encryption standard system. In a practical cryptographic device, security sensitive PDN regions can be identified, significantly reducing the number of the on-chip sensors.


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Kenarangi, F., & Partin-Vaisband, I. (2019). Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(2), 769-781. doi:10.1109/TCSI.2018.2872567


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