ILIEV-DISSERTATION-2020.pdf (5.84 MB)
Algorithm-Hardware Co-design for Low-Power Smart Home AI Devices
thesis
posted on 2020-05-01, 00:00 authored by Nikolai IlievRecent advances in CMOS VLSI technology have enabled the tremendous growth of devices at the
edge of the cloud and in indoor environments: IoT indoor appliances, mobile indoor medical assistants,
mobile indoor manufacturing platforms, indoor drone assistants, and others. As anticipated, this growth
(in edge-device numbers and capabilities) is generating large communications and data processing workloads
for the servers in the cloud. One approach to help manage this trend is to make the edge-nodes
more intelligent and able to process more data onboard (within the edge-node) before communicating
with the servers. This thesis proposes hardware accelerator solutions to three types of onboard (within
platform) processing: Spatial Self-Localization (SSL) which localizes the platform in space, Speaker
Recognition (SpkrRec) which allows human voice control of the platform and authentication of the
human speaker, and Fully-Connected layer evaluation in Neural Networks ( FC-NN ) for accelerated
neural network processing withing the platform. Onboard processing is assumed to include a multi-core
SoC (CPU/GPU), conventional SRAM and DRAM memory as well as high bandwidth memory, HBM
or 3D-DRAM, and communication and sensing subsystems. The SSL, SpkRec, and FC-NN accelerators
can be integrated with the SoC’s peripheral bus structures such as AXI-Stream, AXI-Lite, AXI-HBM,
JESD235A, JESD235B, GPMC, DMA, and similar high-speed processor interfaces.
History
Advisor
Trivedi, Amit RChair
Trivedi, Amit RDepartment
Electic and Computer EngineeringDegree Grantor
University of Illinois at ChicagoDegree Level
- Doctoral
Degree name
PhD, Doctor of PhilosophyCommittee Member
Paprotny, Igor Rao, Wnjuung Metlushko, Vitali Zhang, Zhao Subramanian, ArunSubmitted date
May 2020Thesis type
application/pdfLanguage
- en