An Innovative AMBA Compliant Crossbar Scheme and its Fault Tolerance Analysis

The recent trend in the semiconductor industry to increase the number of computing cores on a single microprocessor has encountered a bottleneck in processor to memory communication bandwidth. To ensure that higher parallelism could be achieved between processing elements and memory banks, the old fashioned shared bus topology for on-chip intercommunication is not sufficient anymore. Alternative topologies have been proposed. The classical bus architecture is often replaced by a crossbar switch type interconnection where cores can simultaneously access memory banks and I/O modules, increasing paral- lelism. Through this thesis we will study the LEON 3 processor architecture and study a way to increase the speed of the intercommunication network used by LEON 3 systems. We will adapt ARM’s Advanced Microcontroller Bus Architecture (AMBA) High-performance Bus (AHB), which is the protocol used by LEON 3 and which is inherently implemented as a multiplexed bus, to work with a crossbar-switch structure instead. The resulting module, named AHB Crossbar Controller, will replace the existing AHB Controller and will maintain compatibility with existing AMBA AHB devices. We will then test the circuit’s fault tolerance to Single Event Upset faults to study its reliability in critical applications. This thesis work is finally intended to be part of a bigger project which aims to the creation of multi-processing partitioned systems. Such systems would include multiple core-memory couples executing in parallel, enabling, through the means of an hypervisor, to have several computing environments running concurrently in these logical partitions. The final objective of this future project is to provide a software alternative to hardware fault- tolerance methods, like radiation hardening, by concurrently running redundant computing environments in a partitioned system and checking via software for correctness.