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Efficient High Performance FPGA-Based Applications Design via SDAccel

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posted on 19.10.2016, 00:00 authored by Lorenzo Di Tucci
Custom hardware accelerators are widely used to improve the performance of software appli- cations in terms of execution times and to reduce energy consumption. However, the realization of a hardware accelerator and its integration into the final system is a difficult and error prone process. For this reason, both industry and academy are continuously developing Computer Aided Design (CAD) tools to assist the designer in the development process. Although many of the steps of the design are now automated, system integration, SW/HW interfaces definition and drivers generation are still almost completely manual tasks. The latest tool by Xilinx how- ever, aims at improving the hardware design experience by automating the majority of the steps in the design flow and by leveraging the OpenCL standard to enhance the overall productivity and to enable code portability. This work provides an analysis and an overview of the new Xilinx SDAccel framework, comparing its design flow to other state of the art frameworks. In this context we use this tool to accelerate two case studies from the bioinformatics field. The first case study concerns pairwise alignment and the second one the protein folding problem. The work is organized as follows: • We start with an introduction to our work, followed by a brief introduction to the context and our contributions in Chapter 1.• Chapter 2 gives the reader an overview of Field Programmable Gate Arrays (FPGAs), followed by an introduction to the Hardware Design Flow (HDF). The chapter ends with a theoretical introduction of the two case studies that we developed. • Chapter 3 describes some state of the art tools used in the design of hardware applications, comparing them and highlighting the main features of each. • Chapter 4 analyzes the problem presented in this dissertation. It starts by describing the design for HPC and ends by talking of how new CAD tools aims at automating the steps of the hardware design flow. • Chapter 5 introduces the tool we used to accelerate our case studies: SDAccel. It starts with an introduction to the framework, then it introduces its architecture and its main features. Finally, it discusses how we faced the problems of the tool and our contributions to its development. • Chapter 6 describes how we decided to accelerate the two case studies introduced in Chapter 2. It explains the architectural choices that we’ve made, as well as the reasons that lead us to choose them. • Chapter 7, presents the results of the two case studies, the experimental settings and the comparison of our result with state of the art implementation of the same algorithm. • Finally, in Chapter 8 we draw the conclusions of this work and we provide some insights into possible future work.

History

Advisor

Rao, Wejing

Department

Computer Science

Degree Grantor

University of Illinois at Chicago

Degree Level

Masters

Committee Member

Gmytrasiewicz, Piotr Santambrogio, Marco

Submitted date

2016-08

Language

en

Issue date

19/10/2016