Emerging Memory System Design to Improve Memory Reliability and Energy Efficiency

Fabrication technology scaling has drastically improved DRAM cell density and thus capacity. However, because shrinking memory cells are less stable and reliable than before, the trend also negatively impacts memory system reliability, security, energy efficiency, and performance. This thesis defense will present three research works to help address those challenges. First, we have designed discreet-PARA, a novel defense mechanism against DRAM rowhammer attacks. The latter is a new security attack that exploits weak DRAM cells by disturbing them with intensive memory accesses to their neighbor rows. The proposed design uses a hybrid of the existing counter-based approach and probabilistic approach. It has very high defense strength, low performance overhead, meanwhile, a small and fixed hardware overhead. It is the first one of this type. Second, we identified a disturbance correlation problem for ECC memory under the rowhammer attack and then proposed a highly efficient scheme to break this correlation. With this new scheme, ECC becomes another layer of defense against rowhammer attacks, drastically improving the overall defense strength. Finally, to address the ever-increasing DRAM refresh energy consumption in high-density DRAM memories, we have designed adaptive dual-refresh, a retention-aware DRAM refresh mechanism. It uses dual and independent refresh mechanisms, namely auto-refresh and target refresh, for DRAM cells of short and long retention times, respectively. The design is novel in that it can make fine-grain adjustments to the auto-refresh period for a given DRAM memory system to maximize energy-saving.