Engineering Interfaces in Polycrystalline CdTe Solar Cells with High carrier Concentration

Arsenic doping of cadmium telluride (CdTe) solar cells has been a subject of increasing interest in the CdTe community. The higher hole densities compared to Cu doping allow for higher built-in potentials and thus higher open circuit voltage (Voc). However, incorporation of As in CdTe absorbers comes with its own set of challenges, and Vocs in real devices have not reached the values that modeling shows to be possible. Arsenic is known to self-compensate in CdTe; as hole densities increase, the formation of donor defects becomes more thermodynamically favorable, compensating the AsTe acceptors. Additionally, with a more highly doped absorber, device performance becomes more dependent on interface parameters such as emitter doping, conduction band offset (CBO), and interface recombination velocity. It therefore becomes critical to optimize the interface and the region surrounding it to minimize recombination effects. In this thesis, methods of engineering both sides of the front interface in CdTe solar cells are discussed. First, the stability of different transparent conducting oxide (TCO) layers are investigated to assess their resilience to various CdTe processing conditions. Maintaining high emitter doping such that ND(emitter) >> NA(absorber) is critical, and it is shown that the electron density of the commonly used emitter layer MgZnO (MZO) is unstable under high temperatures and oxidizing environments. The addition of Ga to MZO is shown to improve the stability. The absorber side of the interface is then discussed, with device modeling showing the impact of compensating donors in the near-interface region of the CdTe absorber. It is suggested that As incorporation be significantly reduced in this portion of the device. To this end, experimental work is presented which has succeeded in inhibiting As accumulation at the front interface through annealing of the initially undoped portion of the absorber. Larger initial grain sizes are correlated with reduced interfacial As, improved junction quality, and higher average Voc. By maintaining a highly doped emitter and managing the absorber doping near the interface, I present possible pathways toward bridging the gap between modeling and experiment in CdTe device performance.