Exploring eBPF Capabilities with Hardware Acceleration on FPGAs for High-Performance Networking

As networked systems increasingly demand lower latency and higher throughput, driven by trends such as cloud computing, real-time analytics, and high-frequency trading, FPGA-based solutions offer a powerful way to offload and accelerate data processing. Their reconfigurability, parallelism, and fine-grained control make them well-suited not only for meeting performance needs but also for being modified to ensure compatibility with new releases. This thesis investigates how to combine high-level programming models with low-level FPGA architectures to enable efficient, scalable, and maintainable network offload from CPUs to SmartNICs. Specifically, it explores the integration of OpenNIC, an open-source FPGA-based SmartNIC platform for AMD-Xilinx Alveo boards, with Nanotube, a suite of compiler passes, libraries, and Application programming interfaces to facilitate the execution of eBPF/XDP—the de facto standard for Linux kernel programming—and similar networking code directly on an FPGA in a seamless and flexible way. The primary objective is to design a unified programming model that simplifies the deployment of high-performance packet processing applications across software and hardware. This required developing an infrastructure that ranges from operating systems to network hardware while optimizing both latency and throughput. This integration presented significant challenges, including maintaining data consistency, ensuring correctness across different bus implementations, and sustaining stable, high-frequency data flow. These difficulties stem from the low-level nature of FPGA design, where timing constraints and coordination between different interfaces must be carefully managed to ensure reliability and correctness. To evaluate the solution, a set of representative XDP applications was tested both in simulation and on two FPGA boards, configured as sender and receiver. The experiments showed a maximum improvement of 404× in latency (measured in clock cycles) and throughput exceeding 100 Gbps. Although performance varied by application, these results underscore the potential of this unified framework for accelerating real-world applications. Finally, I present potential future directions to extend Nanotube’s capabilities, aiming to enhance multi-interface compatibility, improve metadata handling, and increase flexibility for high-performance networking across diverse use cases. This research exclusively used machine-generated datasets, with no human subjects involved.