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FPGA Implementation Of An LDPC Decoder And Decoding Algorithm Performance

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thesis
posted on 24.10.2013, 00:00 authored by Luigi Pepe
In this work the Low Density Parity Check (LDPC) codes have been introduced and described as very powerful error correcting codes. The whole Thesis has been divided in 5 Chapters: in the first Chapter a generical introduction to Block Codes has been provided, followed by a more deeply description about LDPC codes. In the second Chapter the attention has been posed on the decoding algorithms and decoding architectures that are mostly used in practical cases. Then in the third Chapter a new kind of LDPC decoding architecture has been proposed, while in the fourth Chapter several MATLAB simulations results are shown to explain the behaviour of the different decoding algorithms and their performances. The last Chapter is about the conclusions and eventual improvements to both the presented decoder implementation and to the decoding algorithms used.

History

Advisor

Borth, David E.

Department

Electrical and Computer Engineering

Degree Grantor

University of Illinois at Chicago

Degree Level

Masters

Committee Member

Schonfeld, Dan Vecchi, Giuseppe

Submitted date

2013-08

Language

en

Issue date

24/10/2013

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