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Download fileFPGA Implementation Of An LDPC Decoder And Decoding Algorithm Performance
thesis
posted on 2013-10-24, 00:00 authored by Luigi PepeIn this work the Low Density Parity Check (LDPC) codes have been introduced and described as very powerful error correcting codes. The whole Thesis has been divided in 5 Chapters: in the first Chapter a generical introduction to Block Codes has been provided, followed by a more deeply description about LDPC codes. In the second Chapter the attention has been posed on the decoding algorithms and decoding architectures that are mostly used in practical cases. Then in the third Chapter a new kind of LDPC decoding architecture has been proposed, while in the fourth Chapter several MATLAB simulations results are shown to explain the behaviour of the different decoding algorithms and their performances. The last Chapter is about the conclusions and eventual improvements to both the presented decoder implementation and to the decoding algorithms used.
History
Advisor
Borth, David E.Department
Electrical and Computer EngineeringDegree Grantor
University of Illinois at ChicagoDegree Level
- Masters
Committee Member
Schonfeld, Dan Vecchi, GiuseppeSubmitted date
2013-08Language
- en