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FPGA Implementation of an LDPC Encoder

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thesis
posted on 25.10.2015 by Antonello Tartamo
This thesis work introduces linear codes and low-density parity-check (LDPC) codes. It describes some LDPC families that will be used throughout this thesis. Moreover, it shows the main encoding techniques for LDPC codes. After that, it describes two FPGA encoder implementations: a block circulant quasi-cyclic encoder and an IEEE 802.11n encoder. The former is used as reference to make a complexity comparison with the latter.

History

Advisor

Borth, David

Department

Electrical and Computer Engineering

Degree Grantor

University of Illinois at Chicago

Degree Level

Masters

Committee Member

Schonfeld, Dan Vecchi, Giuseppe

Submitted date

2013-08

Language

en

Issue date

24/10/2013

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