FPGA Implementation of an LDPC Encoder
thesisposted on 25.10.2015, 00:00 by Antonello Tartamo
This thesis work introduces linear codes and low-density parity-check (LDPC) codes. It describes some LDPC families that will be used throughout this thesis. Moreover, it shows the main encoding techniques for LDPC codes. After that, it describes two FPGA encoder implementations: a block circulant quasi-cyclic encoder and an IEEE 802.11n encoder. The former is used as reference to make a complexity comparison with the latter.