Hardware Aware Study of Near-Term Quantum Algorithms

Problems predicted to have a clear quantum advantage often involve using quantum algorithms with a black box, or oracle, that encapsulates the solution. The engineering of quantum processors has accelerated to push beyond the near-term intermediate scale. As such, there is growing interest in studies of fundamental black box algorithms tailored to specific hardware designs to verify a quantum advantage experimentally. This thesis explores the Deutsch-Jozsa and Quantum Permutation algorithms as foundational problems in the context of various photonic and cloud-accessible transmon-based platforms that are expected to have a computational advantage over classical implementations. First, we examined the Deutsch-Jozsa (DJ) algorithm implemented on a miniaturized metastructure-based quantum algorithm emulator (QAE) with an inverse-designed graded-index lens for operation in the THz frequency range. In the DJ problem, an oracle assesses a binary function f with n-bit values as input and outputs 0 or 1. The proposed QAE consists of two main components: the oracle subblock, which modulates the phase of the transmitted THz wave, and the Fourier subblock, composed of a GRIN lens to display the desired output signal. We evaluated the structure using numerical simulations and employed inverse design machine learning to validate and optimize parameters such as thickness and hole radii to enhance performance. As a result of this process, the initial design of the GRIN lens was improved for the full-width half-maximum and amplitude of the output THz wave, yielding the expected quantum advantage in the THz regime. Next, we performed a hardware-aware study to implement the Quantum Permutation Algorithm (QPA) on cloud-accessible quantum processors. The QPA aims to determine the parity of an unknown permutation in a single measurement. Previous investigations of this algorithm were restricted to a single 5-qubit processor, which achieved an average success rate of 86% for 2- and 3-qubit circuits. In this thesis, we show the implementation of higher qubit processors up to 127 qubits and assess the impact of current hardware characteristics such as available gate sets, qubit topology, error, etc. We analyze the resource requirements for 2-, 3-, 4- and 5-qubit circuits, including qubit connectivity, circuit depth, and gate fidelity, to identify bottlenecks in execution. Our results demonstrate the feasibility of QPA for small-scale (n=5 and 7) and intermediate-scale (n=127) qubit quantum devices while highlighting the limitations posed by noise and limited coherence times for larger circuits. Through hardware-aware optimizations, including efficient decomposition of multi-qubit Toffoli gates and error mitigation strategies such as dynamical decoupling, we explore pathways for improving QPA performance. This study provides insights into the adaptability of quantum algorithms for near-term devices. It underscores the need for continued quantum software and hardware advancements to unlock quantum computing's full potential.