Heterogeneous Machine Learning Circuits For Nanoscale ICs

Machine learning (ML) is widely used on-chip within many different applications to solve complex problems. While the ML based systems can be very advantageous, they consume considerable power and area. This especially is a critical concern in resource limited applications. In this work, we propose solutions at various design levels to increase the efficiency of on-chip ML systems. At the circuit level, several analog single-transistor matrix-multiplication schemes are proposed that leverage various transistor technologies (such as independent double gate FinFET, triple-well CMOS, and ambipolar carbon nanotube FETs) to enable power and area efficient multiplication under various technological constraints. With these novel schemes, two operands of the multiplication are fed into two individual transistor's input pins, resulting in output current which magnitude is proportional to the product of the input signals. To extract the key tradeoffs and parameters in design of these systems, an automation framework is proposed for fast synthesis of the systems. Finally, our state-of-the-art MAC ICs are exploited alongside CMOS volatile memories, to design a fully analog on-chip training and inference system. The analog trainer exhibits orders of magnitude higher power efficiency and speed and similar accuracy as compared with the digital training solutions.