Multiobjective Reconfiguration-Aware Scheduling on FPGA-Based Heterogeneous Architectures

Designing applications for heterogeneous systems, like Multiprocessor Systems on Chip with Field Programmable Gate Arrays is a complex task. In order to exploit all the capabilities of these systems, such as Partial Dynamic Reconfiguration and hardware acceleration, the designer still has to develop large parts of the system unassisted, establishing the design choices mostly on his experience. In this work we present a Mixed Integer Linear Programming formulation for mapping and scheduling applications on heterogeneous and reconfigurable devices taking into account partial dynamic reconfiguration, module reuse and reconfiguration prefetching. Since the better these techniques and features are exploited, the better is the resulting schedule, and taking into account that the space of the solutions is considerable, it is necessary the use of automatic tools in order to help the system designer in building the best possible application design with respect to his needs, which often are not limited to improve the overall execution time (like most of the other schedulers in the literature do), but to also consider the peak power and energy consumption of the design. This means addressing a specific Resource Constrained Project Scheduling problem, which takes into consideration the reconfiguration aspects with a focus on power and energy metrics that are becoming crucial in designing applications targeting heterogeneous architectures.