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PolyFPGA: A Tool to Automatically Accelerate Iterative Stencil Loops

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posted on 01.07.2016 by Giulio Stramondo
A wide range of scientific problems can be solved using stencil computations. Many particle interaction, computer vision algorithms as well as methods for solving Partial Differential equation are based on stencil computations. Therefore many studies have been done over the years in order to accelerate those kind of algorithms. The aim of this work is to introduce a framework, PolyFPGA, that allows in a completely automatic way to accelerate stencil computations. The framework focuses on the Iterative Stencil Loops (ISL), a type of scientific computation, and generates a streaming-based microarchitecture, known in literature as Streaming Stencil Time-step (SST), that can be synthesized on Field Programmable Gate Array. The SST-based architectures have shown interesting properties of scalability and data reuse, that permits it to be implemented using a low amount of resources. In order to obtain such architecture automatically, the framework leverages some of the mainstream Polyhedral tools, that are smoothly included, and also drives the synthesis using the Xilinx Vivado suite. The framework extends the methodology to generate SST already present in literature, addressing and solving some concrete problems that arise in the automatic generation of the architecture. It was built in a modular manner in order to allow it to target different FPGA boards and to be easily extended with new features and boards.

History

Advisor

Rao, Wenjing

Department

Computer Science

Degree Grantor

University of Illinois at Chicago

Degree Level

Masters

Committee Member

Lillis, John Santambrogio, Marco

Submitted date

2016-05

Language

en

Issue date

01/07/2016

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