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Scalable Multi-bit Precision Compute-in-Memory on Embedded-DRAM

thesis
posted on 01.05.2021, 00:00 by Shruthi Jaisimha
The traditional Von-Neuman architectures consume an enormous amount of energy due to the data movement to and from the memories. This unnecessary energy cost can be obviated by using other novel techniques which can perform the operations on the operands right at the source. There are several works in addressing this issue by using In-Memory Computing techniques which still face challenges due to power-hungry DACs and high precision ADCs. The proposed In-Memory computing architecture is based on state of the art Embedded Dynamic Random Access memories (eDRAM) which uses a new kind of operator called Multiplication free operator. This work is an effort in realizing energy-efficient and compact CiM architecture which is DAC free even for high precision operation The CiM implementation using eDRAM cells is desirable as the SRAM-based CiM framework has a high cell area which limits the memory footprint for on edge devices.

History

Advisor

Trivedi, Amit Ranjan

Chair

Trivedi, Amit Ranjan

Department

Electrical and Computer Engineering

Degree Grantor

University of Illinois at Chicago

Degree Level

Masters

Degree name

MS, Master of Science

Committee Member

Rao, Wenjing Zhu, Zhichun

Submitted date

May 2021

Thesis type

application/pdf

Language

en

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