Priority-Based Memory Access Scheduling for CPU-GPU Workloads

This thesis work is developed to design and implement a brand new Memory Access Scheduling Algorithm for CPU-GPU heterogeneous architectures. The ultimate goal is to introduce a new strategy that would improve the overall performance in real world scenarios, exploiting diverse memory patterns. Due to the complexity of having two modules executing very different workloads, many considerations have to be taken into account when dealing with these systems. For this reason, a considerable part of this work introduces many concepts, previous researches and simulation tests to provide all the necessary knowledge to understand the fundamentals behind the concept of the Priority-Based Scheduling Algorithm. The main idea behind this new strategy is to develop an Algorithm that improves the performance of the whole system in fixed conditions defined by previous works and architectural analysis`. From this basis, the scheduling mechanism has been built developing dedicated architectural features to support a logic that would reflect the environment of interest. Introducing Priority-Based queuing structures and implementing operations able to provide Fairness and different latency values according to the issuing modules, it was possible to achieve a logic able to improve performance in an environment defined by the previously assumed conditions. The design of this new strategy is presented and described starting from a high level architectural point of view, to the implementation layer. Finally, the simulation results are presented and discussed, highlighting the advantages and trade-offs of this new scheduling algorithm.